1. Field of the Invention
The present invention relates to a semiconductor device suited for small-sized elements and a manufacturing method of the same. The present invention relates to, in particular, a semiconductor device capable of preventing impurity concentration from varying in the neighborhood of a pn junction surface and a manufacturing method of the same.
2. Description of the Related Art
It is conventionally necessary to form a pn junction for most of semiconductor devices. In case of an n-channel MIS field effect transistor (metal insulator semiconductor field effect transistor), for example, an n-type source region and an n-type drain region are formed at the surface of a p-type semiconductor substrate. Thus, the pn junctions are formed between the substrate, and the source region and the drain region, respectively. In case of an npn-type bipolar transistor, an n-type emitter region is formed to come in contact with a p-type base region, the p-type base region is formed to come in contact with an n-type collector region. Thus, the pn junctions are formed between the emitter region and the base region and between the base region and the collector region, respectively.
In a semiconductor device having such pn junctions, if the impurity concentration of an n-type region is set higher than that of a p-type region, a pn junction is normally formed by the following method. First, p-type impurities (boron, indium or the like) are injected into a predetermined region of a substrate. N-type impurities (arsenic, phosphorous, antimony or the like) having a concentration higher than that of the p-type impurities are injected only into a region to form an n-type region by means of ion implantation or thermal diffusion. If n-type impurities are injected by means of ion implantation, heat treatment is conducted to activate the impurities. As a result, a pn junction in which the impurity concentration of the n-type region is higher than that of the p-type region, can be formed.
In case of forming an n-channel MIS type FET, in particular, a pn junction is normally formed by the following method. First, p-type impurities are injected into a semiconductor substrate. A gate insulating film is formed on the surface of the semiconductor substrate and a gate electrode is formed on the gate insulating film. Using the gate electrode as a mask, n-type impurities are injected into the surface of the semiconductor substrate by ion implantation. Thereafter, to activate the impurities, heat treatment is conducted. As a result, an n-type source region and an n-type drain region are formed in the region in which the n-type impurities are injected. Obviously, in either case, it is necessary to conduct heat treatment after injecting impurities so as to thermally diffuse or activate the impurities.
If a pn junction is formed by the above-stated method, however, or if a pn junction (n+/p junction) consisting of a p-type region into which boron as p-type impurities is injected and an n-type region having a higher impurity concentration than that of the p-type region, in particular, the spatial distribution of boron is changed by heat treatment. This disadvantageously results in the deterioration of the characteristics of semiconductor elements. This phenomenon does not cause a serious problem to a conventional large-sized semiconductor element. As for recent small-sized semiconductor elements or an MIS-type FET, in particular, it is, however, well known that the variation of the spatial boron distribution has considerably adverse effect on semiconductor element characteristics (D. K. Sadana et al.,: xe2x80x9cEnhanced Short Channel Effects in NMOSFETs due to Boron Redistribution Induced by Arsenic Source and Drain Implantxe2x80x9d, IEDM Technical Digest, IEEE, 1992, pp. 849-852).
That is to say, if a pn junction consisting of a p-type region into which boron is injected and an n-type region having a higher impurity concentration than that of the p-type region is formed, boron is absorbed into the n+ region during heat treatment. Due to this, boron concentration is reduced in the vicinity of the boundary line of the n+/p junction in the p-type region. If this phenomenon appears in an n-channel MIS-type FET, boron concentration between the source and drain regions is reduced. The reduction of boron concentration is more conspicuous if the distance between the source and drain regions, i.e., a channel length is shorter. Thus, a short channel effect, i.e., the phenomenon that the shorter the channel, the lower the threshold of the FET, is higher, making it difficult to form elements having very small (short channel) dimensions. This phenomenon is particularly serious if an MIS type FET having a channel length of 0.1 xcexcm or less is formed.
Considering the above, there is proposed a method of manufacturing a field effect transistor to form a source region and a drain region by means of Halo injection or pocket injection (Japanese Patent Application Laid-Open Nos. Hei 6-244196, 8-330587 and 9-181307). FIGS. 1A and 1B are cross-sectional views showing the structure of a conventional semiconductor device.
As shown in FIGS. 1A and 1B, an element separation insulating film 26 is formed at the surface of a semiconductor substrate 21. Boron is injected into regions defined by the element separation insulating film 26 and a p-type element region is formed. Also, a gate insulating film 25 and a gate electrode 24 on the gate insulating film 25 are formed. First n-type regions 23a for putting a channel region below the gate electrode 24 between themselves are formed at the surface of the element region.
Furthermore, a boron injection region 22a or 22b into which boron ions are implanted is formed at a channel region side contacting with the n-type region 23a in the element region. A sidewall insulating film 27 is formed on the sidewall of the gate electrode 24. N-type impurity ions are implanted into regions which are not covered with the sidewall insulating film 27 and the second n-type region 23b deeper than the n-type region 23a is formed. Thus, a source-drain region 23 consisting of the n-type regions 23a and 23b is formed.
In the conventional semiconductor device constituted as stated above, the boron injection region 22a or 22b is formed by ion implantation so as to protrude the region toward the channel region side of the n-type region 23a and 23b. The boron injection region 22a or 22b is formed by, for example, oblique ion implantation for implanting ions into the element region from the oblique direction with respect to a direction perpendicular to the surface of the substrate 21.
FIG. 2 is a graph showing the distribution of impurity concentration at the surface of the semiconductor substrate shown in FIG. 1A, while the vertical axis indicates impurity concentration and the horizontal axis indicates the position of the semiconductor substrate. In FIG. 2, a broken line 36 indicates the concentration of p-type impurities injected into the surface of the semiconductor substrate 21, a dashed line 34 indicates the concentration of n-type impurities at the surface of the semiconductor substrate 21. A solid line 35 indicates the concentration of p-type impurities at the surface of the semiconductor substrate 21 after heat treatment.
As shown in FIG. 1A, in the conventional semiconductor device, the boron injection region 22a is formed so as to protrude the region 22a toward the channel region side of the n-type region 23a or 23b. Therefore, the neighborhood of the boundary line of the n+/p junction in the p-type region has a higher boron concentration than the remaining portions in the p-type region. Owing to this, boron isabsorbed into the highly doped n+ region by heat treatment and boron concentration of the neighborhood of the boundary line of the n+/p junction in the p-type region is reduced. Further, boron concentration is increased in the neighborhood of the boundary line of the n+/p junction in the n+ region. Even if a lower concentration portion 32 and a higher concentration portion 33 are formed, it is possible to prevent the occurrence of a short channel effect to the transistor. Namely, in the conventional semiconductor device shown in FIGS. 1A and 1B, the boron injection regions 22a and 22b are formed to correct concentration distribution by the addition of concentrations.
Meanwhile, as shown in FIGS. 1A and 1B, to offset the lowered concentration of the lower concentration portion 32 by making boron concentration high in the neighborhood of the boundary line of the n+/p junction in the p-type region in advance, it is necessary to protrude the boron injection region 22a or 22b toward the channel region side of the n-type region 23a or 23b by about several tens of nanometers in width with high accuracy.
The thickness and width of the boron injection regions 22a and 22b are, however, difficult to control independently. According to the oblique ion implantation susceptible to the shape of the sidewall of the gate electrode 24, it is difficult to protrude the boron injection regions 22a and 22b by about several tens of nanometers in width with high accuracy. In addition, since boron in the p-type region is diffused faster than in the n+ region, boron that is injected to protrude toward the p-type region is easily absorbed into the n+ region or diffused into the p-type region during heat treatment.
As can be understood from the above, in the conventional semiconductor device shown in FIGS. 1A and 1B, the lowered concentration of the lower concentration portion 12 cannot be strictly offset even with the boron injection regions 22a and 22b formed to protrude toward the p-type region. As a result, the irregular distribution of boron concentration occurs as indicated by the solid line 35 in FIG. 2. Further, even if the method of forming the boron injection regions 22a and 22b is employed, it is not possible to suppress the formation of the higher concentration portion 33 in the n-type region. This means that the boron ion implanted region cannot be controlled with high accuracy even with the conventional method of simply adding impurity concentrations. Besides, since boron diffusion is difficult to control, it is not possible to sufficiently suppress the occurrence of a short channel effect.
It is, therefore, an object of the present invention to provide a semiconductor device and a manufacturing method of the same capable of preventing impurity concentration from varying in the neighborhood of a pn junction plane, preventing a threshold from lowering by a short channel effect and obtaining good element characteristics.
According to one aspect of the present invention, a semiconductor device may comprise a first conductivity type region, a second conductivity type region formed to contact with the first conductivity type region, and a lightly doped second conductivity type region formed in the second conductivity type region and having a lower net impurity concentration than that of the second conductivity type region. A concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type.
According to another aspect of the present invention, a semiconductor device may comprise a first conductivity type region, a gate insulating film selectively formed on the first conductivity type region, a gate electrode formed on the gate insulating film, and a channel region formed below the gate electrode at a surface of the first conductivity type region. The semiconductor device may further comprise second conductivity type source-drain regions formed in regions putting the channel region between themselves, and lightly doped source-drain regions formed in the second conductivity type source-drain regions, respectively, and having a lower net impurity concentration than that of the second conductivity type source-drain regions. Concentration distributions are formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped source-drain regions.
It should be noted that xe2x80x9ca net impurity concentrationxe2x80x9d means an impurity concentration obtained by subtracting a concentration of the first conductivity type impurity from that of the second conductivity type impurity in the region.
The first conductivity type region may be formed at a surface of a semiconductor substrate.
According to another aspect of the present invention, a semiconductor device manufacturing method may comprise the steps of injecting first conductivity type impurities into a semiconductor substrate to selectively form a first conductivity type region, injecting second conductivity type impurities into a predetermined region in the first conductivity type region, the second conductivity type impurities being higher in concentration than that of the first conductivity type impurity to selectively form a second conductivity type region, and selectively injecting first conductivity type impurities into the second conductivity type region to selectively form a lightly doped second conductivity type region. By the step, a concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region.
According to another aspect of the present invention, a semiconductor device manufacturing method may comprise the steps of injecting first conductivity type impurities into a semiconductor substrate to selectively form a first conductivity type region, injecting first conductivity type impurities into a predetermined region in the first conductivity region to form a highly doped first conductivity type region having a higher impurity concentration than that of the first conductivity type region, and injecting second conductivity type impurities into a region surrounding the highly doped first conductivity type region to change the highly doped first conductivity type region to a lightly doped second conductivity type region and to form a second conductivity type region surrounding the lightly doped second conductivity type region. By the step, a concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region.
The manufacturing method may comprise a step of forming a gate electrode on the first conductivity type region after the step of forming the first conductivity type region. The second conductivity type region may be obtained by injecting second conductivity type impurities by ion implantation while the gate electrode is used as a mask.
The lightly doped second conductivity type region may be obtained by injecting first or second conductivity type impurities by ion implantation while using the gate electrode as a mask.
Moreover, the first conductivity type impurities are, for example, boron impurities.
In the conventional semiconductor device, a second conductivity type region is formed by injecting second conductivity type impurities higher in concentration than first conductivity type impurities into a predetermined region in the first conductivity type region, into which the first conductivity type impurities has been injected. After forming a pn junction by such a method, if heat treatment or the like, for example, is conducted, the first conductivity type impurities are absorbed into the second conductivity type region side in the vicinity of the interface of the first conductivity type region with the second conductivity type region, i.e., in the vicinity of the pn junction part. As a result, the concentration of the first conductivity type impurities decreases. If the concentration of the first conductivity type impurities decreases in the vicinity of the pn junction part in the first conductivity region, the deterioration of the characteristics of the semiconductor device, such as the decrease of a threshold voltage value due to a short channel effect, occurs.
According to the present invention, by contrast, the concentration distribution of the first conductivity type impurities is adjusted so that the concentration of the first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region. Therefore, even if the first conductivity type impurities are absorbed by the second conductivity type region side and the concentration of the first conductivity type impurities decreases in the vicinity of the pn junction part in the first conductivity type region, the first conductivity type impurities are diffused from the lightly doped second conductivity type region into the region, in which the impurity concentration is lowered. Thus, the flow of the first conductivity type impurities is offset and it is, therefore, possible to prevent the concentration of the first conductivity type impurities in the first conductivity type region from decreasing. As a result, if the present invention is applied to, for example, an MIS type FET, it is possible to suppress the occurrence of a short channel effect and to thereby obtain a semiconductor device having excellent characteristics.
Furthermore, according to the method of the present invention, compared with other methods of preventing the decrease of impurity concentration, in which the first conductivity type impurities are injected, in advance, into a region in which the concentration of the first conductivity type impurities is lowered, there is no to strictly control the range of forming the lightly doped second conductivity type region and the concentration distribution. Hence, it is possible to easily manufacture a semiconductor device having excellent characteristics.